In particular because in integrated circuits transistor size continues to decrease under the 100 nm bar by virtue of the advance of technologies such as the CMOS SOI technology, the power consumption associated with static leakage currents is becoming increasingly significant with respect to overall integrated-circuit consumption.
A plurality of techniques, such as power source switching and the use of transistors having a plurality of threshold voltages, commonly called multi-threshold CMOS (MTCMOS) transistors in the art, have been adopted to decrease the consumption associated with static leakage current.
However, these techniques could not preserve data, for example during an integrated-circuit power-source interruption.
Under these circumstances, synchronous retention flip-flop circuits are generally used in order not only to decrease the consumption due to static leakage currents, but also to prevent the loss of stored data.
Conventionally, such a synchronous retention flip-flop circuit uses, during a phase of restoring data, at the end of a phase of retaining data, two storage stages, for example two latch stages that operate alternatively and successively on one of the two (low/high) states of one or more clock signals.
However, a solution with two storage stages generally requires the one or more clock signals and the associated control signals to be routed over very complex pathways. Sometimes such solutions require additional routing via the top metallization levels of the integrated circuit, this multiplying the complexity of the design of this type of synchronous flip-flop circuit.
There is accordingly a need in the art to provide a low-complexity technical solution that uses a small silicon area to make designing synchronous retention flip-flop circuits easier, especially with respect to the routing of the clock and control signals.